Modern electronic devices often include built-in self-testing (BIST) logic to support a variety of tests on the device circuitry. For example, many modern processors contain memory arrays commonly employed to buffer data between one or more system components. As memory array technology continues to improve, the speed and accuracy of testing these memory elements has become increasingly important. Many typical memory BIST systems and/or methods test single memory arrays through a separate test circuit, generally located on a distant part of the chip relative to where the memory array is located, that provides data and address control during self-test operations.
In particular, many systems employ array built-in self-testing (ABIST) logic to perform certain tests on memory arrays within the system. However, typical test configuration designs can increase problems associated with signal routing within the system, and can increase the design complexity of the circuits to be tested. Additionally, many self-test configurations require additional test circuits, which can also increase design time and complexity. Moreover, in systems that also employ logic built-in self-testing (LBIST) functionality, the interface between the LBIST domain and the ABIST domain can become significantly complicated and/or convoluted, thereby requiring even more additional circuitry to stabilize the boundary between the two test domains.
Therefore, there is a need for a system and/or method for memory array manufacturing defect detection that addresses at least some of the problems and disadvantages associated with conventional systems and methods.